AI hardware · Layer

Advanced packaging

Once chips are fabricated, they must be assembled with their memory into a single high-performance package. Techniques like TSMC's CoWoS (chip-on-wafer-on-substrate) join the GPU die and HBM stacks on a shared interposer.

Key facts

Advanced packaging, not wafer fabrication, is frequently the true bottleneck for finished AI accelerators.
CoWoS and similar 2.5D/3D packaging are complex, lower-yield steps that combine multiple expensive dies into one part.
Packaging capacity has been expanded aggressively, but lead times to add it are long.
Because packaging combines the GPU die and the HBM, a shortage of either input, or of packaging itself, stalls the whole part.

Where it bottlenecks

CoWoS-class packaging capacity has repeatedly been the gating step for accelerator shipments, independent of how many GPU dies are fabricated.

Who dominates it

TSMCAmkorASE

Companies in this layer

ASE Group

Taiwan

Outsourced semiconductor assembly and test (OSAT) provider

All companies across the chain

Explore other layers

GPUs and AI accelerators High-bandwidth memory (HBM)Chip foundries and fabrication Lithography and fab equipment Networking and interconnect AI servers and systems Data centers Cooling and thermal management Supply constraints and bottlenecks

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