Who makes
AI chips.

Dominant designer of AI training and inference GPUs, and of the CUDA software stack and NVLink/networking around them.

NVIDIA designs the accelerators most frontier AI is trained on and increasingly sells whole rack-scale systems. Its moat is as much CUDA and the surrounding ecosystem as the silicon. It is a fabless designer: TSMC manufactures the chips.

Designer of Instinct data-center GPUs, the main merchant alternative to NVIDIA for AI compute.

AMD's Instinct line and its ROCm software are the leading challenger to NVIDIA in data-center AI. Like NVIDIA it is fabless and relies on TSMC and on HBM suppliers.

Integrated device maker pursuing a leading-edge foundry business and AI accelerators.

Intel is building out Intel Foundry to offer leading-edge US manufacturing and develops its own accelerators, positioning itself as a domestic alternative across several layers.

Designer of TPU accelerators and a hyperscale AI data-center operator.

Google designs its own TPUs to train and serve its models and runs large AI data centers, making it both a chip designer and an infrastructure operator.

Designer of Trainium and Inferentia accelerators and the largest cloud operator.

Amazon designs Trainium (training) and Inferentia (inference) chips to lower its reliance on merchant GPUs, and operates AI infrastructure at hyperscale through AWS.

Supplier of networking switch silicon and a partner for custom AI accelerators (ASICs).

Broadcom supplies much of the switch silicon that knits AI clusters together and co-designs custom accelerators with hyperscalers, making it central to both networking and bespoke compute.

Designer of wafer-scale AI processors that keep an entire model on one giant chip.

Cerebras builds the largest single chips in the industry: a whole silicon wafer acting as one processor. The bet is that avoiding chip-to-chip communication pays off for training and fast inference. Like most designers, it relies on TSMC for manufacturing.

Designer of the LPU, an inference-only processor built for deterministic, low-latency serving.

Groq targets inference speed rather than training. Its LPU architecture schedules every operation at compile time, which makes latency predictable and high throughput possible for serving LLMs. It sells access mainly through its own cloud.

Designer of the Ascend line of AI accelerators, the leading domestic alternative in China.

Huawei's Ascend chips anchor China's push for AI compute independence under export controls. Manufactured domestically (notably by SMIC) at older process nodes than TSMC's best, they trade peak efficiency for availability inside China.